The present invention relates to the field of data processing, and more particularly to processing signals in a multiple-processor architecture.
Digital signal processors (DSPs) are commonly used in networking equipment to process digitized voice signals. Often, multiple DSPs are arranged in a particular architecture that is selected to meet the needs of a given voice processing application. The exact architecture used is typically influenced by a number of different factors.
One factor that influences a multiple-DSP architecture is the DSPs"" processing power, often represented by a metric called xe2x80x9cMIPSxe2x80x9d (millions of instructions per second). The processing power, or MIPS, of a DSP is determined by a number of factors, including the data width of the DSP, the clock speed of the DSP, the parallel capability of the DSP and so forth. Generally, the greater the processing power of the DSPs in a given architecture, the fewer the number of DSPs need be assigned to a given task.
Another factor that influences a multiple-DSP architecture is the data transfer mechanism in the architecture. For example, in voice processing applications, data is often delivered via a number of time-division-multiplexed (TDM) buses, with individual units of voice data (e.g., voice samples) being transmitted in respective time-slots on one or more of the TDM buses. A multiple-DSP architecture may vary significantly depending on the extent to which TDM buses or other data transfer mechanisms can deliver the data needed for signal processing applications.
A third factor that influences a multiple-DSP architecture is the nature of the signal processing to be performed by the architecture. This factor is closely related to both the data transfer capability of the architecture and to the processing power of the DSPs used in the architecture. For example, a voice compression processing task often requires a relatively larger number of instructions to be executed per data value than does an echo cancellation processing task. Thus, for a given level of data flow on a TDM bus, complex processing tasks usually require greater processing power than do simple processing tasks.
One prior art architecture that is common in voice processing applications involves assigning particular types of processing tasks to specific DSPs in the architecture and coupling the DSPs to either shared TDM buses or dedicated TDM-buses accordingly. For example, DSPs assigned to perform echo cancellation are coupled to respective dedicated TDM buses while DSPs assigned to perform voice compression are coupled to a shared TDM bus. A significant drawback of this approach, however, is that the architecture constrains the types of processing tasks the DSPs can perform, making it difficult to reapply the architecture in the face of changing customer demands or advances in DSP processing capability.
An apparatus and method for data processing in a flexible multiple-DSP architecture that can be readily adapted to changing customer demands and changes in DSP processing capability is described. The apparatus comprises of two or more processors, two or more dedicated serial data buses, and a shared data bus. Each processor processes data received via the dedicated data bus in a first type of processing task. Each processor processes data received via the shared data bus in a second type of processing task.
Other features and advantages of the invention will be apparent from the accompanying drawings and from the detailed description that follows below.